1. Field of the Invention
The present invention generally relates to level converting circuits for converting a logic level of an input signal to a logic level of a different type, and more particularly, to a level converting circuit used in an interface portion of a semiconductor integrated circuit fabricated with a BiCMOS technology.
2. Description of the Background Art
In order to obtain a semiconductor integrated circuit operable at a high speed with low current consumption, a composite integration technology for integrating a bipolar transistor operating at a high speed and a MOSFET (an insulating gate type field effect transistor) having low current consumption on the same semiconductor chip has been conventionally developed. The composite integration technology is referred to as a BiCMOS technology.
When manufacturing a semiconductor integrated circuit having an ECL (Emitter Coupled Logic) interface by using the BiCMOS technology, a bipolar circuit (a circuit having a bipolar transistor as its component) is used as an input/output circuit for external interfacing, and a CMOS circuit (a circuit having a p channel MOS transistor and an n channel MOS transistor as its components) is used as an internal circuit for carrying out desired function When a semiconductor integrated circuit to be manufactured is a memory device, for example, it includes a circuit such as an address buffer and the like as an input/output circuit, and memory cells and a peripheral circuit such as a decoder and the like as an internal circuit.
An ECL level has its high level and low level normally set to -0.9 V and -1.7 V (or -2.1 V), respectively. A signal at the ECL level can be transmitted at a high speed because the small logic amplitude. Therefore, in a system which requires a high speed operation, the signal at the ECL level is used as a signal transmitted between devices.
A CMOS level has a high level substantially equal to one power supply potential VCC and a low level substantially equal to the other power supply potential VEE. The large logic amplitude therebetween makes it possible to reduce power consumption by reliably setting MOSFET to be non-conductive and cutting off a path through which a current flows. Normally, VCC is set to 0 V, and VEE is set to -4.9 V or -5.2 V. The ECL level and the CMOS level are different in the potential level and the logic amplitude. In order to achieve matching of an external signal and an internal signal, level converting function for converting a signal of one logic level into a signal of the other logic level is required in a semiconductor integrated circuit having the ECL interface.
FIG. 9 is a diagram showing a configuration of a conventional cross coupled type level converting circuit for converting an input signal of the ECL level into a signal of the CMOS level. Referring to FIG. 9, a level converting circuit 204 includes a p channel MOS transistor 202 having the gate for receiving an input signal IN of the ECL level applied to an input node N0, the source connected to a first power supply line 9 for transmitting one power supply potential VCC, and a drain connected to an output node N1, a p channel MOS transistor 200 having the gate for receiving a reference voltage (a reference potential), and the source connected to the input node N0, and cross-coupled n channel MOS transistors 201 and 203 for latching a signal potential appearing at the output node N1.
The n channel MOS transistor 201 has its gate connected to the output node N1, the drain connected to the drain of the transistor 200, and its source connected to a second power supply line 10 for transmitting the other power supply potential VEE. The n channel MOS transistor 203 has its gate connected to the drain of the transistor 201, its drain connected to the output node N1, and its source connected to the other power supply line 10.
A reference voltage REF provides a reference for determining high and low levels of the input signal IN, which is normally set to a potential of -2 V to -3 V.
The sizes of the transistors 201 and 203 are made to be slightly smaller than those of the transistors 200, 202. The transistors 201 and 203 may have appropriate current driving capability so as to change the latch state thereof in response to the potential of the input signal IN. Output load driving capability of the level converting circuit 204 is made to be small. This is because it is necessary to make load capacitance associated with the input node N0 small, thereby changing the input signal IN at a high speed. A driver circuit 205 is connected to the output node N1 of the level converting circuit 204. The driver circuit 205 buffers (or inverts and amplifies) an output signal of an MOS level (or the CMOS level) appearing at the output node N1, generates an output signal OUT, and drives a large load at the next stage. Operations will now be described.
An operation when the input signal IN makes transition from the ECL low level (-1.7 or -2.1 V) to the ECL high level (-0.9 V) will be first described. When the input signal IN is at the ECL low level, the transistor 202 is conductive, and charges the output node N1 to one power supply potential VCC. A CMOS (or MOS) high level signal of the output node N1 is latched by a latch circuit configured by the transistors 201 and 203. At this time, the transistor 201 is conductive, while the transistor 203 is non-conductive. The transistor 200 is brought to be conductive when the difference between the gate potential (reference potential) and the source potential (the input signal IN) becomes smaller than a threshold voltage Vtp. Therefore, in this state, the transistor 200 is brought to be substantially non-conductive. The transistor 201 is conductive since it receives a signal of the CMOS level at its gate, and the potential of the drain of the transistor 201 is brought to be the other power supply potential VEE level.
When the input signal IN rises to the ECL high level in this state, the transistor 202 makes transition to the non-conductive state. The transistor 200 makes transition to the conductive state with rise of the source potential, causing the drain potential of the transistor 200 to rise. As a result, the transistor 203 initiates transition to the conductive state, causing the potential of the output node N1 to drop. Responsively, the transistor 201 initiates transition to a non-conductive state. With the transition to the conductive state of the transistor 203 and the transition to the non-conductive state of the transistor 201, the latch state of the latch circuit configured of the transistors 201 and 203 is inverted, and the potential of the output node N1 attains the other power supply potential VEE level of the CMOS low level.
An operation when the input signal IN falls to the ECL low level will now be described. In this case, the transistor 202 makes transition to the conductive state, and initiates charging of the output node N1. With the potential rise of the output node N1, the transistor 201 initiates transition to the conductive state, and the transistor 200 is substantially non-conductive, and therefore the drain potential of transistor 200 begins to drop by the transistor 201, and then transistor 203 makes transition to the non-conductive state. With respective changes in states of the transistors 201 and 203, the latch state of the latch circuit configured of the transistors 201 and 203 changes. As a result, the potential of the output node N1 attains the CMOS high level of one power supply potential VCC level.
The signal appearing at the output node N1 is buffered by the driver circuit 205 to produce an output signal OUT of the CMOS level, driving a load of the next stage.
FIG. 10 is a diagram showing a configuration of a conventional current mirror type level converting circuit for converting the ECL level into the CMOS level. Referring to FIG. 10, a level converting circuit 214 includes a p channel MOS transistor 212 responsive to the input signal IN applied to the input node N0 for charging the output node N1 to one power supply potential (hereinafter referred to simply as a ground potential) VCC level applied to the first power supply line 9, a p channel MOS transistor 210 receiving the reference voltage REF at its gate for detecting the level of the input signal IN applied to the input node N0, an n channel MOS transistor 211 connected between the drain of the transistor 210 and the second power supply line 10, and an n channel MOS transistor 213 provided between the output node N1 and the second power supply line 10. The transistor 211 has its drain connected to each gate of the transistors 211 and 213.
The transistors 211 and 213 configure a current mirror circuit. Operations will now be described.
Description will first be given of an operation when the input signal IN rises from the ECL low level to the ECL high level. When the input signal IN is at the ECL low level, the transistor 212 is conductive, while the transistor 210 is substantially non-conductive. Since little current flows through the transistors 211 and 213 in this state, the output node N1 is at the CMOS high level of the ground potential VCC. The potential of the output node N1 is transmitted to a circuit of the next stage as the output signal OUT through a driver circuit 215. As a result, a large load of the next stage is driven at a high speed.
When the input signal IN rises from the ECL low level to the ECL high level, the transistor 212 makes transition to the non-conductive state, while the transistor 210 makes transition to the conductive state. As a result, a current flows through the transistor 211, and a mirror current is produced also in the transistor 213 accordingly. The potential of the output node N1 is discharged to a negative potential VEE (the other power supply potential is referred to as a negative potential hereinafter) at a high speed, causing the potential of the output node N1 to attain the CMOS low level.
When the input signal IN falls from the ECL high level to the ECL low level, the transistor 212 begins to be conductive, while the transistor 210 begins to be non-conductive. Since the mirror current by the transistor 213 is not produced, the output node N1 attains the CMOS high level through the transistor 212.
FIG. 11 is a diagram showing a configuration of a conventional complementary data input/output current mirror type level converting circuit for converting the ECL level into the CMOS level. A level converting circuit 300 shown in FIG. 11 includes a level converting circuit 31 responsive to ECL level input signals a, /a complementary to each other for providing a complementary output signal /b of the CMOS level, and a level converting circuit 302 responsive to the input signals a, /a for providing an output signal b of the CMOS level. The output signal /b and the output signal b are signals of the CMOS level complementary to each other.
The level converting circuit 301 includes a p channel MOS transistor 220 responsive to the input signal /a applied to an input node N10 for supplying a current from a ground line 9 to a node N15, a p channel MOS transistor 222 responsive to the input signal a applied to an input node N11 for supplying a current from the ground line 9 to an output node N12, an n channel MOS transistor 221 provided between the node N15 and a negative potential line 10, and an n channel MOS transistor 223 provided between the node N12 and the negative potential line 10.
The transistors 221 and 223 configure a current mirror circuit, and amount of supply current flow thereof is determined by the potential of the node N15.
The level converting circuit 302 having the same configuration as that of the level converting circuit 301 includes a p channel MOS transistor 224 for receiving the signal a applied to the input node N11 at its gate, a p channel MOS transistor 226 for receiving the input signal /a applied to the node N10 at its gate, and n channel MOS transistors 225 and 227 configuring a current mirror circuit. The transistor 224 charges a node N16 from the ground line 9 in response to the input signal a applied to the input node N11, and the transistor 226 charges an output node N13 from the ground line 9 in response to the input signal /a applied to the input node N10.
The complementary output signal /b and the output signal b are provided from the output node N12 and the output node N13, respectively. Operations of the level converting circuits 301 and 302 are similar to that of the level converting circuit 214 shown in FIG. 10, and therefore, operations of only one level converting circuit 301 will be described briefly.
When the input signal a changes to the ECL high level, and the input signal /a changes to the ECL low level, the transistor 222 makes transition to the nonconductive state, and the transistor 220 makes transition to the conductive state. As a result, the node N15 is supplied from the ground line 9 with a current, which in turn flows to the negative potential line 10 through the transistor 221. A current of the same amount as that in the transistor 221 flows through the transistor 223. Since the node N12 is not supplied with a current from the ground line 9, the signal /b provided from the output node N12 attains the CMOS low level of the negative potential VEE level.
When the input signal /a is at the ECL high level, and the input signal a is at the ECL low level, the transistor 220 becomes non-conductive and the transistor 222 becomes conductive. Since a current does not flow through the transistor 221 at this time, the transistor 223 becomes substantially non-conductive, causing no mirror current. As a result, the output node N12 is charged through the transistor 222, and the output signal /b attains the CMOS high level of the ground potential VCC level.
FIG. 12 is a diagram showing a configuration of a conventional complementary data input/output cross coupled type level converting circuit for converting the ECL level into the CMOS level. Referring to FIG. 12, a level converting circuit 310 includes a p channel MOS transistor 230 responsive to the input signal /a of the ECL level applied to an input node N21 for charging an output node N23 to the ground potential VCC, a p channel MOS transistor 233 responsive to the input signal a of the ECL level applied to an input node N22 for charging an output node N24 to the ground potential VCC level, and n channel MOS transistors 231, 232, 234 and 235 activated in response to the input signals /a and a applied to the input nodes N21 and N22 for configuring a cross coupled type latch circuit for latching the potentials of the output nodes N23 and N24.
The n channel MOS transistor 231 has its gate connected to the input node N21, its drain connected to the output node N23 and its source connected to a node N26. The transistor 232 has its gate connected to the output node N24, its drain connected to the node N26, and its source connected to the negative potential line 10. The transistor 234 has its gate connected to the input node N22, its drain connected to the output node N24, and its source connected to a node N25. The transistor 235 has its gate connected to the output node N23, its drain connected to the node N25, and its source connected to the negative potential line 10. Operations will now be described.
Description will be given first of an operation when the input signal a rises from the ECL low level to the ECL high level. When the input signal a is at the ECL low level, the output signals b and /b are at the CMOS low level and the CMOS high level, respectively. In this state, the transistor 235 is non-conductive, and the transistor 232 is conductive, while the transistor 231 is conductive, and the transistor 234 is non-conductive.
When the input signal a rises from the ECL low level to the ECL high level, the transistor 233 makes transition to the non-conductive state, while the transistor 230 makes transition to the conductive state. As a result, the node N23 is charged to the ground line 9 through the transistor 230, causing the potential to increase. The transistor 235 begins to make transition to the conductive state, and the transistor 234 is rendered conductive by the input signal a, causing the potential of the node N24 to decrease. The transistor 231 is non-conductive, and accordingly, the transistor 232 initiates transition to the non-conductive state. As a result, a latch circuit configured of the transistors 231, 232, 234 and 235 carries out a latch operation, causing the potentials of the nodes N23 and N24 to change, and the output signals b and /b attain the CMOS high level and the CMOS low level, respectively.
When the input signal a changes from the ECL high level to the ECL low level, the transistors 233 and 230 are rendered conductive and non-conductive, respectively, while the transistors 231 and 234 make transition to the conductive state and the non-conductive state, respectively. As a result, the potentials of the nodes N23 and N24 begin to change in accordance with transition of the input signal a from the high level to the low level, the change is latched by the latch circuit configured of the transistors 231, 232, 234 and 235, and the output signals b and /b attain the CMOS low level and the CMOS high level, respectively.
As described above, the conventional level converting circuits both of a cross coupled type and a current mirror type carry out charging and discharging of the output nodes at the CMOS level in accordance with input signals of the ECL level, thereby carrying out conversion of a signal of the ECL level into a signal of the CMOS level.
The level converting circuits shown in FIGS. 11 and 12 may be provided at the succeeding stage with a driver circuit or a buffer circuit, which in turn is configured to buffer the complementary output signals b and /b to drive a load of the succeeding stage.
The conventional level converting circuits shown in FIGS. 9 and 10 use the reference voltage (reference potential) for determining the potential level of the input signal. The reference voltage is internally generated or externally applied. The transistor for receiving the reference voltage at its gate is rendered conductive or non-conductive in accordance with the difference between the potential level of the input signal and the reference voltage. Therefore, when the reference voltage varies, the latch circuit (in the case of the cross coupled type level converting circuit) and the current mirror circuit (in the case of the current mirror type level converting circuit) are not able to carry out operations in accordance with the potential level of the input signal, so that output signals corresponding to the input signals cannot be provided.
In the cross coupled type level converting circuit, when the sizes of the transistors configuring the latch circuit become inappropriate in value because of variation of manufacturing process parameters (processing temperature, misalignment of mask and the like), the latch state of the latch circuit does not change in response to the input signal, so that output signals corresponding to the input signals cannot be provided.
When the sizes of the transistors of the latch circuit become somewhat inappropriate in value, even although the latch state can be inverted, the switching speed of the latch state may become slower, hindering a level converting circuit from operating at a high speed.
When the size of the transistor receiving the reference voltage and that of the transistors configuring the latch circuit become inappropriate in value, even if the transistor receiving the reference voltage is rendered conductive/non-conductive in accordance with input signals, the latch state of the latch circuit does not change, hindering implementation of precise level converting function. This goes for a transistor for charging an output node which receives an input signal.
In the case of the current mirror type level converting circuit, although the transistor receiving the reference voltage (reference potential) at its gate is rendered conductive/non-conductive in response to the potential level of the input signal, the transistor is not rendered non-conductive completely even if the input signal is at the ECL low level. In other words, even if the input signal is at the ECL low level, the potential difference between the gate and the source of the transistor is in the vicinity of the threshold voltage. Since one of the transistors configuring the current mirror circuit has the gate and the drain connected to each other and operates as a diode, a current path is formed so that current may flow through the current mirror circuit. Therefore, a problem is caused that the power consumption in the level converting circuit becomes larger.